Researchers have built a 32-bit RISC-V processor using a monolayer of molybdenum disulfide (MoS₂), a two-dimensional semiconductor. This achievement demonstrates the potential of 2D materials for creating extremely thin and energy-efficient transistors, pushing the boundaries of Moore's Law. While slower and larger than state-of-the-art silicon chips, this prototype represents a significant step towards practical applications of 2D semiconductors in computing. The processor, dubbed RV16XNano, successfully executed instructions and represents a promising foundation for future development of more complex and powerful 2D-material-based circuits.
The blog post details the author's experience porting Rust to the RockPro64 (RP2350) single-board computer. They successfully brought up a minimal Rust environment, including core libraries, allowing basic "Hello, world!" functionality and interaction with GPIO pins. The process involved building a custom cross-compilation toolchain based on a pre-built Debian image, navigating architectural differences like the lack of an MMU, and implementing necessary drivers. While challenging, this achievement lays the groundwork for more complex Rust development on the RP2350, potentially opening doors for embedded systems applications.
HN commenters generally express enthusiasm for Rust's increasing viability on embedded platforms, particularly the RP2040. Several users discuss the benefits of Rust's memory safety and performance in this context, comparing it favorably to C/C++. Some point out the challenges of working with Rust on resource-constrained devices, like managing memory allocation and dealing with abstractions that can add overhead. A few commenters also mention specific crates like rp-pico and embassy, highlighting their usefulness for embedded Rust development on the RP2040. There's also discussion around build times, tooling, and the learning curve associated with Rust, with some suggesting that the ecosystem is still maturing but rapidly improving. Finally, some users share their own experiences and projects using Rust on embedded systems.
Wokwi now offers a web-based simulator for developing and debugging embedded Rust programs. This online tool allows users to write, build, and run Rust code targeted for various microcontrollers, including the AVR ATmega328P (like the Arduino Uno) and RP2040 (Raspberry Pi Pico), directly in the browser. The simulator features peripherals like LEDs, buttons, serial output, and an integrated logic analyzer, enabling interactive hardware simulation without requiring physical hardware. Code can be compiled and flashed to the virtual microcontroller, and the simulator provides a debugging environment for stepping through code and inspecting variables. This simplifies the embedded Rust development process, making it more accessible for learning and experimentation.
HN commenters generally expressed enthusiasm for Wokwi's online embedded Rust simulator. Several praised its ease of use and accessibility, noting it lowers the barrier to entry for embedded development. Some highlighted the educational benefits, particularly for those new to Rust or embedded systems. A few pointed out the limitations of simulation compared to real hardware, but acknowledged the simulator's value for initial development and testing. The discussion also touched on potential improvements, including support for more microcontrollers and peripherals, as well as integration with other tools. Some users shared their positive experiences using Wokwi for specific projects, further reinforcing its practical usefulness.
Kartoffels v0.7, a hobby operating system for the RISC-V architecture, introduces exciting new features. This release adds support for cellular automata simulations, allowing for complex pattern generation and exploration directly within the OS. A statistics module provides insights into system performance, including CPU usage and memory allocation. Furthermore, the transition to a full 32-bit RISC-V implementation enhances compatibility and opens doors for future development. These additions build upon the existing foundation, further demonstrating the project's evolution as a versatile platform for low-level experimentation.
HN commenters generally praised kartoffels for its impressive technical achievement, particularly its speed and small size. Several noted the clever use of RISC-V and efficient code. Some expressed interest in exploring the project further, looking at the code and experimenting with it. A few comments discussed the nature of cellular automata and their potential applications, with one commenter suggesting using it for procedural generation. The efficiency of kartoffels also sparked a short discussion comparing it to other similar projects, highlighting its performance advantages. There was some minor debate about the project's name.
The "R1 Computer Use" document outlines strict computer usage guidelines for a specific group (likely employees). It prohibits personal use, unauthorized software installation, and accessing inappropriate content. All computer activity is subject to monitoring and logging. Users are responsible for keeping their accounts secure and reporting any suspicious activity. The policy emphasizes the importance of respecting intellectual property and adhering to licensing agreements. Deviation from these rules may result in disciplinary action.
Hacker News commenters on the "R1 Computer Use" post largely focused on the impracticality of the system for modern usage. Several pointed out the extremely slow speed and limited storage, making it unsuitable for anything beyond very basic tasks. Some appreciated the historical context and the demonstration of early computing, while others questioned the value of emulating such a limited system. The discussion also touched upon the challenges of preserving old software and hardware, with commenters noting the difficulty in finding working components and the expertise required to maintain these systems. A few expressed interest in the educational aspects, suggesting its potential use for teaching about the history of computing or demonstrating fundamental computer concepts.
T1 is an open-source, research-oriented implementation of a RISC-V vector processor. It aims to explore the microarchitecture tradeoffs of the RISC-V vector extension (RVV) by providing a configurable and modular platform for experimentation. The project includes a synthesizable core written in SystemVerilog, a software toolchain, and a cycle-accurate simulator. T1 allows researchers to modify various parameters, such as vector register file size, number of functional units, and memory subsystem configuration, to evaluate their impact on performance and area. Its primary goal is to advance RISC-V vector processing research and foster collaboration within the community.
Hacker News users discuss the open-sourced T1 RISC-V vector processor, expressing excitement about its potential and implications. Several commenters praise its transparency, contrasting it with proprietary vector extensions. The modular and scalable design is highlighted, making it suitable for diverse applications. Some discuss the potential impact on education, enabling hands-on learning of vector processor design. Others express interest in seeing benchmark comparisons and exploring potential uses in areas like AI acceleration and HPC. Some question its current maturity and performance compared to existing solutions. The lack of clear licensing information is also raised as a concern.
SiFive's P550 is a high-performance RISC-V CPU microarchitecture designed for applications needing high single-threaded performance. It achieves this through a deep, out-of-order execution pipeline with a 13-stage front-end and a 7-stage back-end. Key features include a large reorder buffer, sophisticated branch prediction, and a high-bandwidth memory subsystem. While inheriting some features from the P550's predecessor (the U74), the P550 boasts significant IPC improvements, increased clock speeds, and enhanced vector performance, positioning it competitively against Arm's Cortex-A75. The microarchitecture prioritizes performance density, aiming to deliver high throughput within a reasonable area footprint.
Hacker News users discuss SiFive's P550 microarchitecture, generally praising its performance and efficiency gains. Several commenters note the clever innovations, like the register renaming scheme and the out-of-order execution improvements. Some express interest in seeing comparisons against Arm's Cortex-A710, while others focus on the potential of RISC-V and its open-source nature to disrupt the established processor landscape. A few users raise questions about the microarchitecture's power consumption and its suitability for specific applications, such as mobile devices. The overall sentiment appears positive, with many anticipating further developments and wider adoption of RISC-V based designs.
TinyZero is a lightweight, header-only C++ reinforcement learning (RL) library designed for ease of use and educational purposes. It focuses on implementing core RL algorithms like Proximal Policy Optimization (PPO), Deep Q-Network (DQN), and Advantage Actor-Critic (A2C), prioritizing clarity and simplicity over extensive features. The library leverages Eigen for linear algebra and aims to provide a readily understandable implementation for those learning about or experimenting with RL algorithms. It supports both CPU and GPU execution via optional CUDA integration and includes example environments like CartPole and Pong.
Hacker News users discussed TinyZero's impressive training speed and small model size, praising its accessibility for hobbyists and researchers with limited resources. Some questioned the benchmark comparisons, wanting more details on hardware and training methodology to ensure a fair assessment against AlphaZero. Others expressed interest in potential applications beyond Go, such as chess or shogi, and the possibility of integrating techniques from other strong Go AIs like KataGo. The project's clear code and documentation were also commended, making it easy to understand and experiment with. Several commenters shared their own experiences running TinyZero, highlighting its surprisingly good performance despite its simplicity.
VexRiscv is a highly configurable 32-bit RISC-V CPU implementation written in SpinalHDL, specifically designed for FPGA integration. Its modular and customizable architecture allows developers to tailor the CPU to their specific application needs, including features like caches, MMU, multipliers, and various peripherals. This flexibility offers a balance between performance and resource utilization, making it suitable for a wide range of embedded systems. The project provides a comprehensive ecosystem with simulation tools, examples, and pre-configured configurations, simplifying the process of integrating and evaluating the CPU.
Hacker News users discuss VexRiscv's impressive performance and configurability, highlighting its usefulness for FPGA projects. Several commenters praise its clear documentation and ease of customization, with one mentioning successful integration into their own projects. The minimalist design and the ability to tailor it to specific needs are seen as major advantages. Some discussion revolves around comparisons with other RISC-V implementations, particularly regarding performance and resource utilization. There's also interest in the SpinalHDL language used to implement VexRiscv, with some inquiries about its learning curve and benefits over traditional HDLs like Verilog.
Summary of Comments ( 39 )
https://news.ycombinator.com/item?id=43621378
Hacker News users discuss the implications of a RISC-V processor built with a 2D semiconductor. Several express excitement about the potential for flexible electronics and extremely low power consumption, envisioning applications in wearables and IoT devices. Some question the practicality due to the current limitations in clock speed and memory integration, while others point out the significant achievement of creating a functional processor with this technology at all. A few commenters delve into the specifics of the fabrication process and the challenges of scaling this technology for commercial production. Concerns about the fragility of the material and the potential difficulty in handling and packaging are also raised. Overall, the sentiment leans towards cautious optimism about the long-term possibilities of 2D semiconductors in computing.
The Hacker News post "A 32-bit processor made with an atomically thin semiconductor" discussing an Ars Technica article about a RISC-V processor built using a 2D semiconductor, generated a moderate number of comments, many of which delve into the technical details and potential implications of the research.
Several commenters focused on the performance aspects. One noted the extremely low clock speed (1 kHz) and questioned the practical applications given this limitation. Another commenter built on this, explaining that the low clock speed is likely due to the high resistance of the thin semiconductor material. They further elaborated that while the transistor density could theoretically be much higher, the interconnect resistance would become a bottleneck.
The discussion also touched upon the challenges of manufacturing and scaling this technology. A commenter pointed out that creating larger, more complex chips using this 2D material would be difficult due to defects. They questioned whether it would be possible to scale this to create a commercially viable product. Another commenter highlighted the specific challenges in achieving uniformity and consistency in a large-scale manufacturing process for atomically thin materials.
The potential advantages of 2D semiconductors were also discussed. One commenter mentioned the possibility of flexible electronics, suggesting that this technology could pave the way for devices that are bendable or even foldable. Another commenter mentioned potential applications in areas where power consumption is extremely important since reducing the thickness to the atomic level can impact a device's energy requirements.
Some comments delved into the specifics of the RISC-V architecture. One commenter pointed out that while the processor is a 32-bit RISC-V design, it lacks features commonly found in modern processors, making it more of a proof-of-concept rather than a practical processor.
Finally, a few commenters expressed skepticism, suggesting that this research, while interesting, is a long way from commercial viability. They emphasized that the current limitations in performance and manufacturing make it unlikely to replace existing silicon technology in the near future.
In summary, the comments section explored the technical complexities, potential benefits, and significant challenges associated with using 2D semiconductors for processor design. While excitement was expressed for the potential of this technology, many commenters remained realistic about the long road ahead for commercialization.