Stories with Tag semiconductor

• Intel doesn't know how to be a foundry," Tim Cook reportedly told TSMC's CEO

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  Posted: 2025-01-29 17:53:53

  Verbose tl;dr

  According to Morris Chang, founding chairman of TSMC, Apple CEO Tim Cook expressed skepticism about Intel's foundry ambitions, reportedly stating that Intel "didn't know how to be a foundry." This comment, made during a meeting where Chang was trying to convince Cook to let Intel manufacture Apple chips, highlights the perceived difference in expertise and experience between established foundry giant TSMC and Intel's relatively nascent efforts in the contract chip manufacturing business. Chang ultimately declined Intel's offer, citing their high prices and lack of a true commitment to being a foundry partner.

  According to a report from Tom's Hardware, citing comments made by Taiwan Semiconductor Manufacturing Company (TSMC) founder Morris Chang during a recent interview, Apple CEO Tim Cook expressed significant doubts about Intel's ability to successfully transition into a competitive foundry business. Chang recounted a conversation he had with Cook, during which Cook purportedly stated, quite bluntly, that Intel "doesn't know how to be a foundry." This remark underscores the immense challenges inherent in the foundry business model, which requires not only cutting-edge semiconductor fabrication technology but also a deep understanding of client needs and a commitment to flexible and responsive customer service. Intel, traditionally focused on designing and manufacturing its own chips, is now attempting to pivot towards becoming a major contract manufacturer for other companies, a strategic shift that places it in direct competition with established foundry giants like TSMC. Cook's alleged comment, as relayed by Chang, highlights the skepticism surrounding Intel's prospects in this highly competitive landscape. The statement suggests that despite Intel's considerable technological prowess and vast resources, the company may lack the specific expertise and cultural mindset necessary to thrive as a contract chip manufacturer, a business that demands a different approach than the internally-focused model Intel has historically employed. This reported conversation offers a glimpse into the high-stakes competition unfolding within the semiconductor industry, as Intel seeks to reinvent itself amidst a rapidly evolving technological landscape and faces established players like TSMC, which has cultivated deep relationships with major clients like Apple over many years.

  • Intel
  • TSMC
  • Tim Cook
  • foundry
  • semiconductor
  • manufacturing
  • chip production
  • Competition
  • Technology Industry
  • Business

  Summary of Comments ( 67 )
  https://news.ycombinator.com/item?id=42868531

  Verbose tl;dr

  Hacker News commenters generally agree with the assessment that Intel struggles with the foundry business model. Several point out the inherent conflict of interest in competing with your own customers, a challenge Intel faces. Some highlight Intel's history of prioritizing its own products over foundry customers, leading to delays and capacity issues for those clients. Others suggest that Intel's internal culture and organizational structure aren't conducive to the customer-centric approach required for a successful foundry. A few express skepticism about the veracity of the quote attributed to Tim Cook, while others suggest it's simply a restatement of widely understood industry realities. Some also discuss the broader geopolitical implications of TSMC's dominance and the US government's efforts to bolster domestic chip manufacturing.

  The Hacker News comments section for the article "Intel doesn't know how to be a foundry," Tim Cook reportedly told TSMC's CEO" contains a moderate amount of discussion, primarily focusing on the complexities and challenges of running a successful semiconductor foundry.

  Several commenters highlight the intricate nature of the foundry business, emphasizing that it's not simply about manufacturing prowess. One commenter points out that building chips for other companies requires a deep understanding of their specific needs and design constraints, suggesting Intel might lack the necessary experience and flexibility in catering to diverse customer requirements. This sentiment is echoed by another commenter who mentions the importance of close collaboration and communication with clients, a skill they believe Intel hasn't honed as much as TSMC.

  The discussion also touches upon the cultural differences between Intel and TSMC. One commenter speculates that Intel's historical focus on internal product development may have fostered a culture less amenable to the demands of external clients. Another commenter suggests that Intel's internal priorities and product roadmaps could potentially conflict with the needs of its foundry customers, creating tension and potentially delaying projects.

  Some comments delve into the technical aspects of foundry operations, discussing the challenges of process technology migration and the importance of yield optimization. One commenter argues that Intel's struggles with its own process nodes might hinder its ability to offer competitive foundry services.

  A few commenters express skepticism about the veracity of the reported conversation between Tim Cook and TSMC's CEO, suggesting it could be a strategic move by TSMC to undermine Intel's foundry ambitions.

  Finally, some comments offer a more nuanced perspective, acknowledging Intel's potential to eventually succeed in the foundry business, but emphasizing the significant hurdles it needs to overcome. One commenter points out that Intel has vast resources and expertise, and with the right investments and strategic adjustments, it could become a formidable player in the foundry market.

• SiFive's P550 Microarchitecture

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  Posted: 2025-01-27 10:32:35

  Verbose tl;dr

  SiFive's P550 is a high-performance RISC-V CPU microarchitecture designed for applications needing high single-threaded performance. It achieves this through a deep, out-of-order execution pipeline with a 13-stage front-end and a 7-stage back-end. Key features include a large reorder buffer, sophisticated branch prediction, and a high-bandwidth memory subsystem. While inheriting some features from the P550's predecessor (the U74), the P550 boasts significant IPC improvements, increased clock speeds, and enhanced vector performance, positioning it competitively against Arm's Cortex-A75. The microarchitecture prioritizes performance density, aiming to deliver high throughput within a reasonable area footprint.

  SiFive's P550, revealed in detail by Chips and Cheese, represents a significant advancement in RISC-V processor microarchitecture, focusing on high performance per watt. It achieves this through a combination of architectural choices and meticulous implementation, targeting a specific performance point rather than blindly maximizing clock speed. The P550 is an out-of-order, superscalar design implementing the RISC-V RV64GC ISA, capable of issuing up to seven instructions per cycle. This high throughput is facilitated by a decoupled front-end and back-end.

  The front-end features a branch predictor, instruction fetch unit, and decoder, feeding a 100-entry instruction queue. This queue is crucial for smoothing out variations in instruction delivery and providing a constant stream of instructions to the back-end. Branch prediction utilizes a tournament predictor with a global history buffer and per-branch history tables, aiming for high accuracy to minimize pipeline stalls. The P550 also features a dedicated return address stack for efficient handling of function calls and returns.

  The back-end is where the out-of-order execution magic happens. A substantial 96-entry reorder buffer tracks instructions as they progress through the pipeline, ensuring correct in-order retirement. The scheduler is responsible for dynamically allocating execution resources to instructions based on availability and dependencies. The P550 boasts a rich set of execution units, including five integer ALUs, two load/store units, and three fully pipelined FPU units capable of handling both single and double-precision operations. These units allow for significant parallel execution of instructions. Furthermore, the physical register file, which holds the actual data being operated on, is generously sized to accommodate the high number of in-flight instructions.

  Memory access is a critical aspect of performance. The P550 incorporates a 64KB L1 instruction cache and a 64KB L1 data cache, both with high bandwidth and low latency. These caches feed into a 512KB unified L2 cache. Misses in the L2 cache are serviced by an external memory interface. Store-to-load forwarding within the pipeline further enhances memory access efficiency by allowing subsequent loads to access data written by preceding stores before they reach main memory.

  A key differentiator for the P550 is its focus on power efficiency. The microarchitecture is designed to minimize power consumption at a given performance level. This is achieved through a combination of clock gating, voltage scaling, and careful optimization of individual components. Furthermore, the relatively conservative clock speed target contributes to lower overall power consumption.

  Finally, SiFive has implemented extensive performance monitoring capabilities within the P550. These capabilities provide detailed insights into the processor's internal operation, allowing for performance analysis and optimization. This data is invaluable for software developers seeking to tune their applications for maximum performance on the P550 architecture. In summary, the SiFive P550 offers a compelling combination of high performance, power efficiency, and a rich feature set, showcasing the potential of the RISC-V architecture in the high-performance computing arena.

  • SiFive
  • P550
  • RISC-V
  • Microarchitecture
  • CPU
  • Processor
  • Computer Architecture
  • Chips and Cheese
  • performance
  • Out-of-Order Execution
  • Superscalar
  • Hardware
  • semiconductor
  • Instruction Set Architecture

  Summary of Comments ( 10 )
  https://news.ycombinator.com/item?id=42839501

  Verbose tl;dr

  Hacker News users discuss SiFive's P550 microarchitecture, generally praising its performance and efficiency gains. Several commenters note the clever innovations, like the register renaming scheme and the out-of-order execution improvements. Some express interest in seeing comparisons against Arm's Cortex-A710, while others focus on the potential of RISC-V and its open-source nature to disrupt the established processor landscape. A few users raise questions about the microarchitecture's power consumption and its suitability for specific applications, such as mobile devices. The overall sentiment appears positive, with many anticipating further developments and wider adoption of RISC-V based designs.

  The Hacker News post discussing the Chips and Cheese article on SiFive's P550 microarchitecture has a moderate number of comments, exploring various aspects of the architecture and RISC-V in general.

  Several commenters focus on the out-of-order execution capabilities of the P550. One commenter questions the complexity of achieving high performance with out-of-order execution, particularly concerning register renaming and branch prediction. They express curiosity about the design choices made by SiFive in these areas and how they compare to established architectures like x86. Another commenter builds on this, emphasizing the challenges in balancing performance, power efficiency, and die area, especially for a relatively new player in the CPU market. They express interest in seeing real-world benchmarks and power consumption figures for the P550.

  A thread of discussion emerges comparing RISC-V to other instruction set architectures (ISAs). One commenter highlights the potential of RISC-V to disrupt the existing landscape, suggesting that its open nature allows for greater innovation and customization. They contrast this with the closed ecosystems of x86 and ARM, arguing that RISC-V fosters a more collaborative and open development environment. Another commenter counters this perspective, noting that the freedom and flexibility of RISC-V can also lead to fragmentation and incompatibility issues. They point out the importance of establishing robust standards and ensuring software ecosystem maturity for RISC-V to truly compete with established ISAs.

  The topic of software support for RISC-V also receives attention. One commenter expresses skepticism about the availability of high-quality compilers and optimized libraries for RISC-V, questioning whether the software ecosystem can keep pace with the rapid hardware development. Another commenter acknowledges these concerns but points to ongoing efforts to improve software support, mentioning projects aimed at porting existing applications and developing new tools for RISC-V. They express optimism about the future of the RISC-V software ecosystem.

  Finally, a few commenters discuss the potential applications of the P550 and RISC-V more broadly. Some suggest that RISC-V is well-suited for embedded systems and specialized applications where customization and power efficiency are paramount. Others envision RISC-V eventually challenging x86 and ARM in the broader computing market, particularly in areas like data centers and cloud computing.

• Impact of Low Temperatures on the 5nm SRAM Array Size and Performance

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  Posted: 2025-01-21 12:17:51

  Verbose tl;dr

  This study investigates the effects of extremely low temperatures (-40°C and -196°C) on 5nm SRAM arrays. Researchers found that while operating at these temperatures can reduce SRAM cell area by up to 14% and improve performance metrics like read access time and write access time, it also introduces challenges. Specifically, at -196°C, increased bit-cell variability and read stability issues emerge, partially offsetting the size and speed benefits. Ultimately, the research suggests that leveraging cryogenic temperatures for SRAM presents a trade-off between potential gains in density and performance and the need to address the arising reliability concerns.

  This SemiEngineering article delves into the intricate effects of extremely low temperatures, specifically cryogenic temperatures, on the performance and physical dimensions of 5nm SRAM arrays. The motivation behind this exploration stems from the increasing interest in specialized computing applications, such as quantum computing and high-performance computing, where operating at cryogenic temperatures can offer significant advantages. These advantages primarily revolve around reduced power consumption and improved performance characteristics of transistors.

  The article highlights the complex interplay of factors at play when SRAM operates in such extreme cold. While lower temperatures generally lead to improved transistor performance due to reduced leakage current and increased carrier mobility, they also introduce new challenges. One key challenge is the variation in temperature coefficients across different components of the SRAM cell, leading to imbalances that can negatively impact stability and reliability. Specifically, the article discusses the differing temperature dependencies of the pull-up and pull-down networks within the SRAM cell, which can cause read and write failures if not carefully managed.

  A central focus of the article is the impact of temperature on the bitcell size. At cryogenic temperatures, the improved transistor performance allows for the use of smaller transistors while maintaining the required stability margins. This reduction in transistor size directly translates to a smaller overall bitcell area, enabling denser SRAM arrays. The article quantifies these size reductions, illustrating the potential for significant area savings at cryogenic temperatures compared to room temperature operation. This densification is particularly crucial for applications like quantum computing, where large SRAM arrays are required for storing quantum states and intermediate computational results.

  Furthermore, the article examines the performance implications of cryogenic operation. While lower temperatures inherently enhance transistor speed, the interconnected nature of SRAM arrays introduces complexities. The article discusses the impact of temperature on interconnect delays, which can become a limiting factor at cryogenic temperatures. It also explores the trade-offs between performance and power consumption, emphasizing the need for careful optimization to maximize the benefits of low-temperature operation.

  Finally, the article touches upon the challenges associated with designing and manufacturing SRAM arrays for cryogenic environments. These challenges include the need for specialized materials and fabrication processes that can withstand the extreme temperatures and ensure reliable operation. The overall message conveyed is that while cryogenic operation offers promising opportunities for enhancing SRAM performance and density, it also presents significant design and engineering hurdles that must be addressed to fully realize its potential. The article effectively paints a picture of a complex landscape where optimizing for cryogenic operation requires a deep understanding of the interplay between transistor physics, circuit design, and thermal management.

  • SRAM
  • 5nm
  • low temperature
  • performance
  • array size
  • semiconductor
  • Chip Design
  • Integrated Circuits
  • cryogenic
  • Memory
  • CMOS

  Summary of Comments ( 12 )
  https://news.ycombinator.com/item?id=42779293

  Verbose tl;dr

  Hacker News users discussed the potential benefits and challenges of operating SRAM at cryogenic temperatures. Some highlighted the significant density improvements and performance gains achievable at such low temperatures, particularly for applications like AI and HPC. Others pointed out the practical difficulties and costs associated with maintaining these extremely low temperatures, questioning the overall cost-effectiveness compared to alternative approaches like advanced packaging or architectural innovations. Several comments also delved into the technical details of the study, discussing aspects like leakage current reduction, thermal management, and the trade-offs between different cooling methods. A few users expressed skepticism about the practicality of widespread cryogenic computing due to the infrastructure requirements.

  The Hacker News post titled "Impact of Low Temperatures on the 5nm SRAM Array Size and Performance" (https://news.ycombinator.com/item?id=42779293) has a moderate number of comments discussing various aspects of the linked article. Several commenters focus on the practical implications of operating chips at extremely low temperatures, especially regarding cost and complexity.

  One compelling thread explores the trade-offs between cryogenic cooling and architectural improvements. A commenter points out that while extreme cooling can offer performance benefits, it introduces significant overhead in terms of refrigeration equipment and energy consumption. They argue that focusing on architectural advancements might be a more efficient approach to performance gains. This sparks further discussion about the potential of specialized hardware designed specifically for low-temperature operation, with some suggesting that certain applications, like high-performance computing, might justify the cost of cryogenic cooling despite these challenges.

  Another significant point of discussion revolves around the article's focus on SRAM. Some commenters question the real-world relevance of SRAM scaling at such low temperatures, highlighting that other components, like DRAM, might present more significant bottlenecks in cryogenic computing systems. They suggest that optimizing the entire system for low temperatures, rather than just focusing on SRAM, is crucial for realizing any meaningful performance gains.

  Several comments also delve into the technical details mentioned in the article. One commenter elaborates on the impact of temperature on leakage current and transistor threshold voltage, explaining how these factors influence SRAM cell stability and overall chip performance at low temperatures. Another comment discusses the challenges of designing and manufacturing circuits that can operate reliably across a wide temperature range, highlighting the potential benefits of specialized fabrication processes for cryogenic chips.

  Finally, some comments express skepticism about the overall significance of the research presented in the article, suggesting that the performance gains achieved through extreme cooling might not be substantial enough to justify the associated costs and complexities. They argue that other approaches to improving chip performance, such as architectural innovations and advanced packaging techniques, might offer more practical solutions.